/*
 * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2020-2023. All rights reserved.
 */

#ifndef __DTS_HI3519DV500_CLOCK_H
#define __DTS_HI3519DV500_CLOCK_H

/*  fixed   rate    */
#define HI3519DV500_FIXED_2400M    1
#define HI3519DV500_FIXED_1200M    2
#define HI3519DV500_FIXED_1188M    3
#define HI3519DV500_FIXED_896M     4
#define HI3519DV500_FIXED_800M     5
#define HI3519DV500_FIXED_792M     6
#define HI3519DV500_FIXED_786M     7
#define HI3519DV500_FIXED_750M     8
#define HI3519DV500_FIXED_700M     9
#define HI3519DV500_FIXED_672M     10
#define HI3519DV500_FIXED_600M     11
#define HI3519DV500_FIXED_594M     12
#define HI3519DV500_FIXED_560M     13
#define HI3519DV500_FIXED_500M     14
#define HI3519DV500_FIXED_475M     15
#define HI3519DV500_FIXED_396M     16
#define HI3519DV500_FIXED_300M     17
#define HI3519DV500_FIXED_297M     18
#define HI3519DV500_FIXED_257M     19
#define HI3519DV500_FIXED_250M     20
#define HI3519DV500_FIXED_200M     21
#define HI3519DV500_FIXED_198M     22
#define HI3519DV500_FIXED_187P_5M   23
#define HI3519DV500_FIXED_150M     24
#define HI3519DV500_FIXED_148P_5M   25
#define HI3519DV500_FIXED_134M     26
#define HI3519DV500_FIXED_108M     27
#define HI3519DV500_FIXED_100M     28
#define HI3519DV500_FIXED_99M      29
#define HI3519DV500_FIXED_74P_25M   30
#define HI3519DV500_FIXED_72M      31
#define HI3519DV500_FIXED_64M      32
#define HI3519DV500_FIXED_60M      33
#define HI3519DV500_FIXED_54M      34
#define HI3519DV500_FIXED_50M      35
#define HI3519DV500_FIXED_49P_5M    36
#define HI3519DV500_FIXED_37P_125M  37
#define HI3519DV500_FIXED_36M      38
#define HI3519DV500_FIXED_27M      39
#define HI3519DV500_FIXED_25M      40
#define HI3519DV500_FIXED_24M      41
#define HI3519DV500_FIXED_12M      42
#define HI3519DV500_FIXED_12P_288M  43
#define HI3519DV500_FIXED_6M       44
#define HI3519DV500_FIXED_3M       45
#define HI3519DV500_FIXED_1P_6M     46
#define HI3519DV500_FIXED_400K     47
#define HI3519DV500_FIXED_100K     48

#define HI3519DV500_I2C0_CLK    50
#define HI3519DV500_I2C1_CLK    51
#define HI3519DV500_I2C2_CLK    52
#define HI3519DV500_I2C3_CLK    53
#define HI3519DV500_I2C4_CLK    54
#define HI3519DV500_I2C5_CLK    55
#define HI3519DV500_I2C6_CLK    56
#define HI3519DV500_I2C7_CLK    57

#define HI3519DV500_SPI0_CLK    62
#define HI3519DV500_SPI1_CLK    63
#define HI3519DV500_SPI2_CLK    64
#define HI3519DV500_SPI3_CLK    65

#define HI3519DV500_EDMAC_CLK   69
#define HI3519DV500_EDMAC_AXICLK   70

/*  mux clocks  */
#define HI3519DV500_I2C0_MUX    72
#define HI3519DV500_I2C1_MUX    73
#define HI3519DV500_I2C2_MUX    74
#define HI3519DV500_I2C3_MUX    75
#define HI3519DV500_I2C4_MUX    76
#define HI3519DV500_I2C5_MUX    77
#define HI3519DV500_I2C6_MUX    78
#define HI3519DV500_I2C7_MUX    79

#define HI3519DV500_FMC_MUX     80
#define HI3519DV500_HPAXI_MUX   81
#define HI3519DV500_DDRAXI_MUX  82
#define HI3519DV500_MMC0_MUX    83
#define HI3519DV500_UART0_MUX   84
#define HI3519DV500_UART1_MUX   85
#define HI3519DV500_UART2_MUX   86
#define HI3519DV500_UART3_MUX   87
#define HI3519DV500_UART4_MUX   88
#define HI3519DV500_UART5_MUX   89

/*  gate    clocks  */
#define HI3519DV500_FMC_CLK     90
#define HI3519DV500_UART0_CLK   91
#define HI3519DV500_UART1_CLK   92
#define HI3519DV500_UART2_CLK   93
#define HI3519DV500_UART3_CLK   94
#define HI3519DV500_UART4_CLK   95
#define HI3519DV500_UART5_CLK   96
#define HI3519DV500_MMC0_CLK    97
#define HI3519DV500_MMC0_HCLK   98
#define HI3519DV500_MMC1_CLK    99
#define HI3519DV500_MMC1_HCLK   100
#define HI3519DV500_MMC2_CLK    101
#define HI3519DV500_MMC2_HCLK   102

#define HI3519DV500_ETH_CLK		103
#define HI3519DV500_ETH_MACIF_CLK	104
#define HI3519DV500_ETH1_CLK		105
#define HI3519DV500_ETH1_MACIF_CLK	106

/*  complex */
#define HI3519DV500_MAC0_CLK		110
#define HI3519DV500_MAC1_CLK		111
#define HI3519DV500_SATA_CLK		112
#define HI3519DV500_USB_CLK		113
#define HI3519DV500_USB1_CLK		114

#define HI3519DV500_MMC1_MUX    115
#define HI3519DV500_MMC2_MUX    116

/* lsadc clocks */
#define HI3519DV500_LSADC_CLK		120

#define HI3519DV500_PWM0_MUX    121
#define HI3519DV500_PWM1_MUX    122
#define HI3519DV500_PWM2_MUX    123

#define HI3519DV500_PWM0_CLK	124
#define HI3519DV500_PWM1_CLK	125
#define HI3519DV500_PWM2_CLK	126

/* pll clocks */
#define HI3519DV500_APLL_CLK		250

#define HI3519DV500_CRG_NR_CLKS		256

#endif	/* __DTS_HI3519DV500_CLOCK_H */

